Understand the architecture of the chip and functional block being designed
- Compose test plan and validation vectors to ensure functional completeness
- Develop verification environments for standalone unit testing and enhance/use the automated regression infrastructure setup for unit level, IP level and full chip functional verification.
- Help debug and correct functional errors in the design blocks, using logic abstraction, simulation and debug tools, based on good understanding of the architectural specification, RTL and/or device level design of the block.
- Build testbench and testcase for power-aware simulation
- Be responsible to mentor and coach the team for greater technical depth in Functional areas as well as the verification methodology improvement and Infrastructure enhancements to support the design environment
- Develop tools or monitors to improve verification
Requirement and Preferred Experience:
- Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Experience with ASIC design or verification
- Understand low power design flow is a plus
- Experience on verilog HDL coding and debugging
- Experience on C/C++ programming and debugging
- Familiar with script(perl, tcl) program and makefile
- Familiar with SystemVerilog
- Experience with USB3.0 Controller and/or PHY design or verification is a plus
- Experience with MIPI Controller and/or PHY design or verification is a plus
- Good communication skill and teamwork spirit
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