- Understand the architecture of the chip and functional block being designed
- Build C/C++ model for simulation
- Build test bench and monitors for DUT
- Compose test plan and validation vectors to ensure functional completeness
- Debug function/performance bugs of graphics chips
Requirement and Preferred Experience:
- Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification
- Should have excellent communication skills (both written and oral)
- Strong problem solving skills
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